1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a reference voltage generating circuit of a nonvolatile ferroelectric memory device.
2. Background of the Related Art
In general, a nonvolatile ferroelectric memory device such as a ferroelectric random access memory (FRAM), for example, has a data processing speed equivalent to that of a dynamic random access memory (DRAM), and the nonvolatile ferroelectric memory device retains data during a power OFF state. Accordingly, the nonvolatile ferroelectric memory devices are commonly considered to be one of a next generation of memory devices.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having high residual polarization characteristics. The residual polarization characteristics permit the retention of data when an applied electric field is removed.
FIG. 1 is a circuit diagram illustrating a cell array according to the related art, FIG. 2 illustrates a unit circuit diagram of a main cell of FIG. 1, and FIG. 3 is a unit circuit diagram of a reference cell according to the related art.
In FIG. 1, a cell array block includes a plurality of sub cell arrays. A sensing amplifier S/A is formed between adjacent top and bottom sub cell arrays sub_T and sub_B. Each of the sub cell arrays includes bitlines Top_B/L and Bot_B/L, a plurality of main cells MC connected to the bitlines Top_B/L and Bot_B/L, a reference cell RC connected to the bitlines Top_B/L and Bot_B/L, and a column selector CS. The reference cell RC within the sub cell array sub_T formed in a top portion of the sensing amplifier S/A is simultaneously accessed when the main cell M/C within the sub cell array sub_B is accessed. On the other hand, the reference cell RC within the sub cell array sub_B formed in a bottom portion of the sensing amplifier S/A is simultaneously accessed when the main cell MC within the sub cell array sub_T is accessed. The column selector CS selectively activates a corresponding column bitline using Y (column) address. If the column selector CS is in high level, the corresponding column bitline is connected to a data bus, so as to enable data transmission.
In FIG. 2, the main cell MC is formed by having a bitline B/T formed in one direction, and a wordline W/L formed to cross the bitline. A plate line P/L is spaced apart from the wordline W/L in the same direction as the wordline W/L. A transistor T with a gate connected to the wordline W/L and a source connected to the bitline B/L is formed. A ferroelectric capacitor FC is formed in such a manner that its first terminal is connected to a drain of the transistor T and its second terminal is connected to the plate line P/L.
In FIG. 3, each of the reference cells of the nonvolatile ferroelectric memory device includes a bitline B/L formed in one direction, a reference wordline REF_W/L formed across the bitline, and a switching block controlled by a signal of the reference wordline to selectively transmit a reference voltage stored in the ferroelectric capacitors bitline. A level initiating block selectively initiates a level of input terminal of the switching block connected to the ferroelectric capacitors. Ferroelectric capacitors FC are formed between a connection node SN of the switching block and the level initiating block and a ground voltage terminal Vss.
The switching block includes an NMOS transistor (hereinafter, referred to as first transistor T1) with a gate connected to the reference wordline REF_W/L, a drain connected to the bitline B/L<n>, and a source connected to a storage node SN.
The level initiating block is controlled by a reference cell pull-up control signal REF_P/U which is a control signal for initiating the storage node SN of the reference cell. Also, the level initiating block includes a PMOS transistor (hereinafter, referred to as second transistor T2) connected between the source of the first transistor T1 and a power source voltage Vcc.
A first electrode of the ferroelectric capacitor is connected to the source of the first transistor T1 and a second electrode is connected to the reference plate line REF_P/L.
The second transistor T2 is turned on upon receiving a “low” signal, thereby initiating the storage node SN to a “high” level.
FIG. 4 is a hysteresis loop illustrating electric charge generation of the reference cell according to the related art. In FIG. 4, a reference level is generated in the bitline by sending out non-switching (destruct) charge Qns of the ferroelectric capacitor to the bitline. The non-switching charge Qns is generated while moving from point b-1 to point b-2.
FIG. 5 illustrates an operation of the reference cell according to the related art, whereby one cycle consists of an active period and a precharge period. The active period begins as a chip enable pad CEBpad is transited to a “low” level, and is completed after passing through the precharge period. Period A is the precharge period of a previous cycle. In addition, when the active period of a chip begins, an address is decoded during period B, and as a plurality of control signals are activated, the reference wordline REF_W/L and the reference plate line REF_P/L are transited from a “low” level to a “high” level. Furthermore, with the beginning of period C, the reference wordline REF_W/L and the reference plate line REF_P/L are sequentially transited from a “low” level to a “high” level, thus a “high” data of the reference cell is transmitted to each bitline. The reference pull-up signal REF_P/U is once again transited to a “low” level during precharge period D. During the other periods, the reference pull-up signal REF_P/U is maintained at a “low” level, thus enabling a storage node SN of the ferroelectric capacitor to be at a “high” state.
The aforementioned related art circuit for generating reference voltage of a nonvolatile ferroelectric memory device has the following disadvantage. In accordance with the operation temperature, the reference level is inconsistent and varies greatly between Qns and Qns*. As the temperature increases, the reference level shows the characteristic of decreasing, thereby decreasing a sensing margin.